
PCI-DSP01 Users Manual (Rev 1.0)
8- http://www.daqsystem.com
♦ 32-Bit/33-MHz Peripheral Component Interconnect (PCI) Master/Slave Interface
Conforms to:
PCI Specification 2.2
Power Management Interface 1.1 Meets Requirements of PC99
− PCI Access to All On-Chip RAM, Peripherals, and External Memory (via EMIF)
− Four 8-Deep x 32-Wide FIFOs for Efficient PCI Bus Data Transfer
− 3.3/5-V PCI Operation
− Three PCI Bus Address Registers:
Prefetchable Memory
Non-Prefetchable Memory I/O
− Supports 4-Wire Serial EEPROM Interface
− PCI Interrupt Request Under DSP Program Control
− DSP Interrupt Via PCI I/O Cycle
♦ Two Multichannel Buffered Serial Ports (McBSPs)
− Direct Interface to T1/E1, MVIP, SCSA Framers
− ST-Bus-Switching Compatible
− Up to 256 Channels Each
− AC97-Compatible
− Serial-Peripheral-Interface (SPI) Compatible (Motorola)
♦ Two 32-Bit General-Purpose Timers
♦ IEEE-1149.1 (JTAG†) Boundary-Scan-Compatible
♦ 288-Pin Micro-Star BGA Package (GHK Suffix)
♦ 3.3-V I/Os, 1.5-V Internal, 5-V Voltage Tolerance for PCI I/O Pins
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