DAQ VXI-SC-1102 Manuál s instrukcemi Strana 31

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Chapter 2 Lab and 1200 Devices
DAQ Hardware Overview Guide 2-4 www.ni.com
Data acquisition timing involves the following timing signals:
•A start trigger is an edge-triggered signal that initiates a data
acquisition sequence. You can supply a trigger pulse either externally
through the I/O connector EXTTRIG input or from software control.
You can enable a hardware start trigger by calling the DAQ function
DAQ_Config or specifying trigger mode in the AI_Start.vi or
AI_Trigger_Config.vi.
•A conversion pulse is a signal that generates a pulse once every sample
interval, causing an A/D conversion to be initiated. This signal can be
generated by the onboard, programmable sample-interval clock
supplied by the 8253 Counter/Timer on the Lab and 1200 device, or
can be supplied externally through the I/O connector EXTCONV*
input. You can select external conversion pulses by calling
DAQ_Config. If you do not want to use external conversion pulses,
you should disconnect the EXTCONV* pin on the I/O connector to
prevent extra conversions.
•A scan interval pulse is a signal that generates a pulse every scan.
The scan clock for interval scanning pulses can be generated by the
onboard, programmable scan-interval counter, or can be supplied
through the OUTB1 pin on the I/O connector.
•A sample counter is used when conversion pulses are generated either
by the onboard sample-interval counter or externally. The sample
counter tallies the number of A/D conversions (samples) and shuts
down the data acquisition timing circuitry when the device has
acquired the desired number of samples.
•A stop trigger is a signal used for pretriggered data acquisition to
notify the Lab and 1200 device to stop acquiring data after a specified
number of samples. Until you apply the stop trigger pulse at the
EXTTRIG input, a data acquisition operation remains in a continuous
acquisition mode, indefinitely writing and rewriting data to the buffer.
You can select pretriggering by calling the DAQ function
DAQ_StopTrigger_Config.
•A timebase clock is a clock signal that is the timebase for the
sample-interval or scan-interval counter. Counter B0 is used to provide
the timebase clock when the interval between samples or updates is
greater than 65,535 µs. The timebase for sample and scan interval is the
same.
See your device user manual for more information regarding these signals.
Note The Lab and 1200 devices use half-FIFO mode by default when doing interrupt data
transfer operations for analog input with rates faster than 1500 S/s. You can select between
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